Serial data transmission is used to transmit and receive data between semiconductor integrated circuits through a few number of data transmission lines. For example, in the case of low voltage differential signaling (LVDS) transmission, serial data and a clock signal synchronized with the serial data are transmitted through their respective signal lines. In this case, transmitting the serial data at a high speed exceeding 1 Gbps is difficult due to the effect of a difference in propagation delay between the serial data and the clock signal.
The clock data recovery (CDR) scheme overcomes the problem of a difference in propagation delay between the serial data and the clock signal since the clock signal is transmitted embedded in the serial data. In the CDR scheme, a clock data recovery (CDR) circuit at the receiving side monitors changing points of the serial data, recovers the clock signal based on the detected changing points, and latches the serial data using the recovered clock signal.
FIGS. 1A and 1B are block diagrams showing a conventional serial data transmission system 1300. In the system 1300 of FIG. 1A, a transmitting circuit 1200 and a receiving circuit 1100 are interconnected via a differential transmission line L1 through which serial data embedded with a clock signal propagates and a return transmission line L2 through which a sequence adjustment signal propagates. The transmitting circuit 1200 transmits a clock signal having a predetermined frequency in a first sequence SEQ1. Upon receiving the clock signal from the transmitting circuit 1200, the receiving circuit 1100 recovers a sampling clock signal at the reception side using the received clock signal. The receiving circuit 1100 acknowledges the reception of the clock signal in the first sequence SEQ1 by transmitting a sequence adjustment signal to the transmitting circuit 1200 via the return transmission line L2. Upon receiving the acknowledgement, the transmitting circuit 1200 proceeds to a second sequence SEQ2 where it transmits the serial data synchronized with the previously transmitted clock signal.
In the system 1300 of FIG. 1A, there is a need to return to the first sequence SEQ1 since no synchronization takes place when the transmitting circuit 1200 or the receiving circuit 1100 is reset during transmission of the serial data.
In the system 1300 of FIG. 1B, the transmitting circuit 1200 and the receiving circuit 1100 are connected via the single differential transmission line L1 and are respectively provided with oscillators 1210 and 1110 to generate reference clock signals having the same frequency. This system does not require the return transmission line L2 but cannot change the transmission rate.